1. Field of the Invention
This invention relates to memory arrays, and in particular to a memory array of flash memory cells having a plurality of sub-arrays separated by metal source lines in which the number of metal source lines is reduced so as to reduce the size of the array
2. Description of the Related Art
The use of non-volatile memories, particularly flash memories, has greatly increased. There are several types of flash memory arrays used in such memories. One type of conventional array 10 is called a NOR-type array as depicted in FIG. 1. The memory cells 38 of the array each include a source, a drain and a channel region intermediate to the source and drain. A floating gate is disposed above, and insulated from the channel region and a control gate is disposed above the floating gate. In order to reduce any ambiguity regarding the distinction between the source and drain, for the N channel memory cells, the drain is defined herein as the element which is positive with respect to the source during memory read operations.
The flash cells 38 are arranged in rows and columns, with each of the cells in a particular row having its control gate connected to a common word line WL.sub.N. All of the cells in a particular column have their drains connected to a common bit line 40. In addition, all of the sources in the array are connected together. Note that some memory systems include arrays having multiple blocks of cells, with the sources of the cells in the same block connected together so as to permit the blocks to be erased separately. When the cells are read, the sources are all usually grounded, with the common designation for ground being V.sub.SS. Thus, the source lines are sometimes referred to as V.sub.SS lines or connections. As will be explained, the array 10 of FIG. 1 is arranged into sub-arrays, including sub-array 11 and sub-arrays 32 and 36 disposed on either side of sub-array 11. Only a single column of sub-arrays 32 and 36 is depicted.
The sources of the cells 38 are typically connected together by way of non-metallic lines 42, such as diffused semiconductor lines, since metal lines occupy a large amount of area. These semiconductor source lines 42 are shown in FIG. 1 running along side the word lines WL.sub.N, with the resistance of the semiconductor source lines being represented by lumped resistors R.sub.S. A source line 42 is shared with two word lines. The semiconductor lines 42 have a much greater resistance as compared to metal lines and such resistance tends to both reduce the effective cell read current and makes cell programming more difficult by either increasing the amount of time required to program the cells and/or requiring higher programming voltage to program the cell. Thus, metal source lines are used in combination with the semiconductor lines so as to reduce the overall source line resistance. As can be seen in FIG. 1, the metal source lines 28, 29 and 30 are effectively connected in parallel with the semiconductor lines.
The metal lines include a plurality of column segments 28 and 30 which extend generally parallel with the columns of cells and a row segment 29 which extends along the bottom of the array interconnecting all of the column segments 28 and 30 together. Typical flash memory arrays may have from 128 to 2048 rows. Typically, a sub-array will have 8, 16 or 32 columns of cells which are disposed intermediate to the metal source line column segments 28 and 30 so as to reduce the number of such metal lines, which, as previously noted, consume a large amount of die area. In the FIG. 1 example, the sub-arrays contain 16 columns of cells 38 between the metal source line column segments 28 and 30.
As previously noted, FIG. 1 shows one memory sub-array 11 and one column of the two adjacent memory sub-arrays 32 and 36. A typical array may have 8, 9, 16, 18, 32 or more of such sub-arrays depending upon further decoding and the number of output pins.
As is well known, in order to read a particular cell 38 it is necessary to apply appropriate voltages to the cell by way of the associated word line WL.sub.0 -WL.sub.N and the associated bit line 40. The common source line is usually grounded. Part of the memory address of the cell to be read provided by an associated processor or the like is decoded in the memory by an X decoder (not depicted) so as to apply a read voltage to the word line WL.sub.N connected to the cell. The remainder of the address is applied to a Y decoder which will connect an appropriate voltage to the bit lines 40 associated with the cell being read. At the same time, a sense amplifier (not depicted) is connected to the bit line 40 for use in sensing the read current.
As can be seen in FIG. 1, the Y decoder (only a small portion of which is disclosed) includes a select transistor N associated with each cell column and connected to the bit line 40 of the column. Each of the 16 select transistors N receives a one of 16 select signal Y.sub.0 -Y.sub.15. Only one of the select signals Y.sub.N is made active at any one time during memory read operations so that only one of the 16 select transistors N connected to the common data line DL.sub.N is turned on during a read operation.
In a typical memory system, each address contain a word of data, with each word having 8, 16 or more bits. If, for example, each word is 8 bits, a single select transistor N will be turned on in 8 separate memory sub-arrays so that a total of 8 bits will be read out in each read operation. For example, the decoded address may cause select signal Y.sub.4 to go active in 8 separate sub-arrays so that 8 bits are simultaneously connected to separate data line DL.sub.N and read out of the memory for a given address.
Typical memory systems also provide that individual cells can be programmed. Such programming sequences are well known and need not be described. However, in such sequences, only one of the cells in a particular sub-array is programmed at one time. Thus, as was true in the case of cell reading, only one select signal Y.sub.N of the 16 signals applied to sub-array 11 is made active in a programming operation. Again, a total of 8, 16 or more bits can be programmed at one time depending upon the length of the individual words.
In many memories, there are a plurality of blocks which can be separately erased, as previously noted. In a typical 4 megabit memory with a 16 bit data bus, there are sometimes blocks as small as 64 Kilobits. Such blocks, with the prior art of reading one output per sub-array, could be organized with no more than 256 rows with 16 columns per sub-array because a minimum of 256 columns (16 columns per sub-array times 16 bits being operated on in parallel) would be required; that is unless, there are less columns per sub-array. Eight columns per sub-array would add twice as many metal source lines to the array, but would then allow this 64 Kilobit array to be organized as 512 rows by 128 columns. With the present invention which allows operating on two bits per sub-array, the 64 Kilobit array could be organized as 512 rows by 128 columns with the sub-array having 16 columns per metal source lines. Thus the invention can result in a saving in the overhead of metal source lines in the array while allowing the array to be organized with twice as many rows.
The present invention functions to reduce the number of metal source lines column segments so as to reduce the area occupied by these metal source lines. This is accomplished without significantly increasing the overall source line resistance so that memory reading and programming is not adversely affected. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.